Optimization for PI: Layout synthesis & Cap selections

In system analysis, signal integrity is done in either pre-layout and post-layout phase. Power integrity (PI), on the other hand, deals with mostly post-layout data. Layout is usually generated manually and then simulated in time consuming 3D solving process. As a result, optimization flow for PI is quite different from that for SI and is also very problem specific.

Power Integrity:

Power delivery model

Power delivery model

Power integrity aims at providing “clean” voltage supply to active elements in the channel such as driver and receiver. A typical representation of power delivery network is shown above, it starts with the voltage regulation and includes the motherboard, the package, and the die itself. Due to the impedance associated with the power delivery loop, any current through this loop will cause a drop in the voltage available to the die. Current is supplied from voltage regulator ultimately but is also stored in the de-coupling capacitors on the conducting path.This drawing current (Icct or Iload) varies due to different number of buffers switching at different frequency or work load… This drop in the voltage at the die directly impacts the maximum operating frequency of the design. Thus a spec. must be provided and met for the droop voltage to assure design quality.

The impedance in the power delivery loop can be classified as both resistive and inductive. The resistive drop is proportional to the current through the loop while the inductive drop is proportional to the rate of change of current. It is desired to have small loop inductance as Ldi/dt will contribute to the droop. This inductive drop is typically countered by adding several stages of decoupling caps at various points in the power delivery network. This helps reduce the overall impedance of the power delivery loop over a broad frequency range.

The conducting paths are layout design, rather than spice-like electrical netlist. The decoupling caps are usually provided by external vendors (e.g. Murata) and the designer needs to decide where and how to place them. So a power integrity analysis usually includes the following aspects:

  • stackup, power via arrangement and pin out;
  • decoupling strategy, choice of location, number and value of caps

Optimization w/ Design synthesis:

The power delivery network is layout design solved with 3D field solver. If designs can be generated via rule-based synthesis, then the design cycle can be shortened and many designs can be generated in advance. A batch-mode like process is then used to solve for different PDN models for comparison and trade-off study.


Take the different on-chip antennas shown above as an example, they are specified with different geometry parameters so that software algorithms is used to synthesize the design quickly. Do so manually may not be accurate or efficient. For a PD design, the rules are much more complicated than just the geometrical based parameters. Nevertheless, best practice or experienced based rules can still be summarized so that algorithm can perform the following tasks automcatically:

  • Modify layer stackup thickness and material properties
  • Generate pin, nodes, traces and shapes on specific layer either based on net name or reference location to other (signal or power) pins
  • Generate (power) vias in certain pattern and connect to power/ground planes. Voids and proper pad-stacks are also generated as part of the process
  • Duplicate certain region of the design (template) to other area as a X-Y array
  • Perform DRC alone the way and generate warnings

The flow mentioned above is purposely built for a certain solver, it’s because different solver has its own definitions for different design object (via, traces, nodes etc) and the layout syntax is also solver specific. Nevertheless, this flow has great potential of shorten design cycle, permit design optimization via quick analysis of different design, and even reduce the needs for engineering layout resources.

Decoupling analysis:

Once decoupling strategy (land side caps and/or die-side caps) and corresponding layout is generated, a S-parameter for the PDN can be obtained via 3D field solving. With proper provision (not stuffing cap in advance in the design), this generated S-parameter may be used directly again and again for what-if decoupling analysis. If there is no layout/stackup change, 3D solving does not need to be repeated.


As shown above, different combination of caps “stuffed” at the output ports will cause impedance seeing into the die ports to vary. Conceptually, one may simulate the given S-parameter with cap connected and measure the impedance using simulation in frequency domain. In practice, such simulation is not needed as S-parameter can be converted into Y/Z-parameters and lumped together with cap’s FD impedance and be analyzed directly. As a result, we can post-process the PDN’s S-parameter for a certain decoupling cap arrangement to gain the following insights very quickly:

  • The impedance (both inductive and resistive) of the PDNLac
  • Current contributed by each de-caps at certain frequencyZIAC
  • Input impedance seen at each die-portZf
  • Effective analysis: by removing a particular de-cap, how much impact does it have to the die’s impedance.ZFCIF
  • How does this compare to different configuration: repeat the same “what-if” analysis for different configuration.

Optimization for SI & PI: Systematic approach

In previous post, we talked about exploring solution space linearly using what-if analysis. When more comprehensive or a near global search for best/worst performance is desired, a systematic approach must be used.

Response surface modeling (RSM):

System output responses Y1, Y2 shown below may have both controllable and uncontrollable input variables X and Z. In system analysis, the output is obtain via circuit simulation mostly and is thus deterministic. As a result uncontrollable factors maybe lumped into constant term and the mapping between controllable factor, X, to its output can be viewed as a multi-dimensional surface like shown in the right below. Search of optimized combination is like searching for maximum or minimum on the curvature.


This type of “mapping” from x to y is called “response surface modeling (RSM). It takes many sampling points to construct such response surface. A design of experiments (DOE) method is often used in this RSM approach.

Design of experiment (DOE):

When more than several variables are involved and each of them has a range of possible values, using full grid (full combination)  to do exhaustive search for best combination is really not feasible.

If a performance measurement, Y, is represented as a function f(x) of design variables x1, x2 ~ xn, then we can use a Taylor series to approximate f(x)

The higher order (bigger value of alpha above) to be included as part of the series, the more accurate it will resemble the original function f(x). It’s a little like decomposing time domain square wave in frequency domain using FFT. In system analysis, just like in many phenomenons in real world, f(x) is dominated by lower order terms. Take two variable and two order maximum as an example, the equation above can be further simplified as the following quadratic form:


Different value of input variables (X1, X2.. etc) will have different output performance Y. When more than several sampling points are taken, then the equations can be written as an matrix form, each row represents a sampling run:


When further generalize to all the variables, a linear system is formed:


With this, one can use linear algebra technique such as pseudo inverse and/or singular value decomposition to solve for coefficients beta such that the error is minimized (optimized) in the mean squared error (MSE) sense.


Using this DOE/RSM methodology, several decisions needs to be made in advacne:

  • Selection of input variable X and order: only dominate variables should be used to minimize the number of columns;
  • Selection of output target Y: output target obtained by mathematical operation (post-processing) may loose the lower order relation to original variable x;
  • Choice of sampling algorithms and number of samples: each row of the matrix corresponds to a “simulation” run, the samples must cover enough design space to make solution meaningful while minimize impact due to the noise of modeling.

DOE analysis flow:

A systematic optimization flow based on DOE/RSM thus includes the following steps:

  • Define variables: only dominate variable should be used in the analysis. A trivial variable will increase the matrix size and have very small coefficient (beta). The selection of dominated variable may be identified from experience, previous analysis run, linear sweep or what-if analysis. The DOE flow may also be performed several times, with non-significant variables being removed at the end of each iteration.
  • Create sampling points: There are several sampling algorithms when choosing sampling points. The choice should be made based on design’s coverage, optimality and efficiency. For SI/PI, when number of variables is around 10, central composite design is a good choice as it is full quadratic with only about 1000 design to run. D-Optimal is a good choice when number of variables is bigger (up to 30). When using neural network for final modeling, full quadratic is not needed and a space filling type design is a good choice. All these designs are available in statistic software package and subset of them have been implemented in our MPro module.


  • Create corresponding test cases: Regardless of the design, a variable’s range needs to be decided. Depending on whether a variable is categorical (non-continuous) or numerical (continuous), possible step value may be decided. A generic representation usually use -1, 0, and 1 in the design table to represent minimum, typical and maximum variable values. Then next step is to translate such settings into corresponding design. For netlist type circuit representation, pattern replacement is sufficient. For geometric synthesis which require further mathematical manipulation using these design variables, a more flexible mapping mechanism should be provided. At the end of the stage, each row of the design table will be translate to a corresponding circuit design in order to be simulated.


  • Simulate and post-processing: A simulation manager is often desired in this step in order to distribute testcases to run on different CPU threads or different machines. A post-process step is executed right after simulation ends to extract performance matrices from the results. Outcome of this step is a row of output measurement for each test case run.


  • Map inputs to outputs:  Form a second or third order equations using defined independent variable, then solve for their coefficients using SVD solver. Residues values which is difference between original response and “predicted” one based on solved formula can then be calculated. A well fit model will have very small residue. A R^2 value, which is the portion of variation attributed to the model can be used to indicate the fit. A R^2 >= 0.95 is usually desired.



  • Optimize: Constraints such as non-negative value and must fall within variable range needs to be imposed. Based on these restriction, solution to minimize or maximizing a cost function, which can be weighted sum of several performance targets, can be searched. Depending on the order of the prediction formula constructed, different type of optimization method can be used:
    • Linear programming: good for formula with only first order variable, which is usually the case for stackup performance based on geometric parameters;
    • Non-linear method: when formula has higher order terms, method like Nelder algorithm may be used;
    • Genetic algorithm: when model is highly non-linear or neural network based, this algorithm is best to search for optimized solution.


  • Prune variables for next iterations: As the variables’ coefficients reveal their significance toward the output Y, some of them may be removed for next iteration analysis. A significance list may also be formed as a reference in the design process.

As one can see, a systematic flow such as DOE/RSM requires much more efforts and intermediate steps comparing to a simple linear sweep or what-if analysis. On the other hand, a well fit prediction model can also be served as a base of quick “what-if” analysis to replace time consuming simulation and be used as an initial guidance when using design variables.

A stackup what-if based on model built via DOE/RSM flow

A stackup what-if based on model built via DOE/RSM flow


Optimization for SI: What-if analysis

Optimization for system performance:

For electrical analysis such as signal integrity, a “system” is usually defined from end to end, i.e. from IO buffers of an IC, going through passive interconnect such as package, traces and vias, then connector or package again down to final receiver. There are many components involved in such a channel. Each of them has their own design parameters, so there are many factors affecting this system’s performance. In addition, there are also different performance matrices, such as eye height, width and timing margin etc. There maybe trade-offs between these performance targets. For example, the largest eye width may not produce the largest eye height, so either one is more preferred than the others or a weighting scheme needs to be used.

Selection_006Sources of noise affecting performance:

While the end goal is to maximize desired performances, they are actually affected by several electrical functions in the form of noise sources. We can imagine variables from individual channel components as x1, x2 ~ xn, these noise function g1(x1, x2), g2(x1, x3..) etc are part of performance function f(g1(x), g2(x)…) = f(x1, x2 ~ xn). This partition usually makes connections between variables and the noise response, i.e. x1, x2 to g(x), more meaningful and easier to understand. Not doing so, the big system function f(x) will have all variables lumped together. Another considerations is that many of the variables are orthogonal to each other, so by lumping strongly coupled ones into same g(x) functions, we reduce the efforts required to search for the whole solution space.

In a system, sources of noise can be categorized roughly as the followings:

  • Inter-symbol interference (ISI): this is usually caused by signal dispersion along the channel and the reflections due to impedance mismatch. A symbol (lone 1 pulse) starting as a nearly square wave at the driver may end up as a distorted one at the receiver due to this interference with itself.
  • Cross channel interference (CCI, or crosstalk): This is caused by inductive and/or capacitive coupling between victim and aggressors, they are mostly dominant at higher frequency and are very material and geometry (relative distance) sensitive. Componentwise, they maybe from on chip source (mainly capacitive) and off chip such as transmission line or vias etc.
  • Power supply noise: Different workload of the buffers may affect the terminal supply voltage. For example, when all buffers are driving, current supply may be limited and thus voltage will drop, and the slew rate will change accordingly as well.
  • Random noise: This is due to thermal noise (usually Gaussian distribution) or other jitters.

By exploring relations between x and g(x), it will help achieving end goal of optimizing f(x).


Optimization approaches:

Giving so many variables  (x1, x2 ~ xn) and either intermediate (g(x)) or final performance (f(x)) functions, how do we find the best xi values such that f(x) will be optimized (either maximize or minimize, by itself or weighted among several f(x)s)?

A channel being designed must have a spec. to meet. Different industry standards such as PCIe GenX, HDMI, SATA, USB, DDR etc each has its own compliance matrices before the designed final product can be certified to use such logo. For a smaller design company or when time to market is a constraint, a designer usually only want to look for “a” solution rather than the best solution. For bigger companies which provide design guides, they may need to do full analysis to make sure even in the worst condition, their product will still functional properly when being used by other companies in their own designs. In addition, perform a “full analysis” usually requires lots of simulations so computing resource available also imposes a constraint. Generally speaking, there are two approaches for system optimization:

  • What-if analysis: In this approach, many of the design variables have been set to a “fixed” value and a designer linearly explore impacts of limited remaining variables to the noise function or performance. Since each variable is adjust linearly, it’s not likely global best/worst values can be found this way. On the other hands, this what-if flow has the following benefits:
    • Can run with limited computing resource;
    • Can find “a” solution more easily and quickly;
    • Can help a designer gaining more insights regarding a variable’s impact on the performance, thus help a better design in the future.
  • Systematic methods: This approach can be considered as “what-if” analysis in multi-dimensions. Much more variables are taking into account with their respective ranges of values (thus still not “global” strictly speaking). The following steps are then taken to find min/max solutions in such a multi-dimension design spaces. (They will be explained in more details in separate post.)
    • Create sampling points:
    • Create corresponding test cases:
    • Simulate and post-processing:
    • Map inputs to outputs:
    • Optimize:
    • Study non-fitted results:

More on what-if analysis:

What-if analysis explores solution spaces linearly and usually provides instant response/feedback to the designer, so the chosen variables should have dominate impact on performances and the channel setup should be simplified. If only ISI and CCI are considered, one may break the aforementioned channel and lump related variables into the following sections to explore individually:

  • Driver: driver’s strength, slew rate, supply voltage, EQ settings
  • Interconnect:
    • transmission lines: layer stackup and materials Dk/Df, trace width, distances and layout etc
    • vias: pad, anti-pad size, barrel width, back-drill etc
    • package/connectors: change of reference and reference impedance etc
  • Receiver: termination scheme and different terminator values, EQ response and settings etc.

Note that driver/receiver variables here are behavioral already rather than original design parameters such as transistor sizing, doping concentration etc. So a behavioral model like IBIS, AMI etc need to come into play. For interconnects, solving transmission line using 2D/2.5D solver based on their physical and geometrical properties are more feasible, comparing to solving those for 3D structures like vias or even connectors.  For these via/connectors, a simplified model may again need to be built and come into play for quick what-if analysis.

Via model into PI model

Via model into PI model based on TDR results

The trade-off:

We think the value of a signal/power integrity engineer is very much on his or her insights on the design variables involved and their impacts to system’s performance. Such insights can be obtained from direct what-if analysis and/or detailed study of prediction model constructed via systematic optimization approach. The pitfall of the later one is that, with established flow and design cycle constraints, an engineer may easily become a “simulation engineer”, who just execute the flow and produce report without detailed study or understanding of interaction between different design variables.

SPISim’s support for system optimization:

With the spirits mentioned in this post in mind, we have flows for both what-if and systematic approaches. In our XPro module, variables in simplified setup has been categorized in advance to explore their impacts on ISI, CCI and power:




Not only will they provide instant analysis results via built-in simulator, the final model can also be generated in place based on the variables’ values used. These features are not available on may other commercial offerings and will be valuable capabilities to a system engineer.