CPro: SPISim’s schematic editor for SI/PI… “C” for “Channel”
- Free form schematic editor with system level focus (IBIS, TLine etc)
- To review/analysis net extracted from post-layout;
- For what-if analysis either interactively or with parameter sweeps;
- Integrate with SPISim’s modules as top-level design cockpits for various modeling (e.g. IBIS, Stackup, T-Line and SParam) performance or quality analysis.
- Schematic editor to build channel from scratch or on-top of existing design;
- Free form editing or from net(s) extracted from post-layout design in NPro
- Hierarchical data structure or data navigation (multi-level subckt)
- System level focused modeling: IBIS with various bit patterns and TLine with simple T-element, W-element or stackup based model generation with HSpice
- Cross-probe with extracted nets from post-layout via NPro
- Seamless integration for device modeling needs:
- IBIS inspector for IBIS management, generate spec-model if needed;
- S-parameter analysis for via, connectors or package models
- Transmission line analysis or predictor for tabular models
- PCB/Package stackup and pad-stack management.
- Netlisting as spice output to simulate interactively or parameter sweep
- Support HSpice or other spice-compatible simulators
- Full factorial, space filling or other what-if simulation plan
- simulate interactively, in batch mode or spice files only for external simulation ;
- For design review with revision control.
MPro: Modeling and Optimization Tool | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation
Module overview: Further details on CPro’s capabilities are available [HERE].
Overview slides: View externally:[HERE]
Video demo: View externally:[HERE]
- Windows, Linux or OSX